A drive circuit of this kind is made on a substrate of an electro-optical apparatus, for example a liquid crystal device, etc., as a data-line drive circuit for driving data lines or a scanning-line drive circuit for driving scanning lines. At the time of the operation thereof, the data-line drive circuit samples an image signal supplied on an image-signal line at the timing of sampling pulses to supply the image signal to the data lines. Here, if the frequency of the driving becomes particularly high, the front edge and the back edge of sampling pulses in succession in time, which are used for sampling, become overlapped slightly. Thus, the image signal to be sampled at different time is overlapped partially, and is supplied to the data lines. As a result, the deterioration of resolution and ghosts occur.
Accordingly, up to now, there has been a technique for regulating each pulse of the sampling pulses by a plurality of series of enable signals selected in sequence in order to achieve high-definition image display in accordance with a high driving frequency. However, if the phase of the sampling pulses is shifted, image signals to be sampled at different time are overlapped all the same, and thus the deterioration of resolution and ghosts sometimes occur. For example, according to the technique described in Patent Document 1, the output (a primary clock signal) of the shift register is shaped by a secondary clock signal to generate sampling pulses in order to use it for the opening and closing of the sampling switch. In this case, the variations of the sampling pulses are absorbed in the variations of the secondary clock signal.    [Patent Document 1] Japanese Unexamined Patent Application Publication No. 8-286640